A digital circuit such as a microprocessor includes numerous transistors that alternate between dormant and switching states. Such digital circuits thus make abrupt current demands when large numbers of transistors switch states. But power supplies cannot react so quickly such that the voltage on the power supply lead or interconnect to the die including the digital system may dip unacceptably. To smooth the power demands, it is conventional to load the power supply lead to the die with decoupling capacitors. The decoupling capacitors store charge that may be released during times of high power demand so as to stabilize the power supply voltage from the external power supply.
It is conventional to mount decoupling capacitors onto a circuit board but such a mounting location increases the circuit board footprint. Moreover, it desirable to place the decoupling capacitor as close as possible to the die it services. Mounting the decoupling capacitor further away from the die onto the circuit board increases the parasitic resistance and inductance undesirably. Thus, it is conventional to surface mount decoupling capacitors onto the package substrate for the die but such a mounting location increases the package substrate footprint. To increase density, it is also conventional to embed capacitors such as decoupling capacitors into the package substrate. The die may be mounted to the package substrate directly over the embedded decoupling capacitor, which advantageously reduces the parasitic resistance and inductance.
Embedded package substrate (EPS) capacitors are typically formed by cutting a hole out of a substrate, placing the capacitor in the core layer, filling the hole with material to hold the capacitor, and then coupling the capacitor to other components using through vias. FIG. 1 illustrates a package substrate 100 with an EPS capacitor 150 according to the prior art. The substrate 100 includes a core layer 102, a cavity 104, and a plurality of metal layers such as an M1 metal layer 106, an M2 metal layer 108, an M3 metal layer 110, and an M4 metal layer 112. EPS capacitor 150, which may comprise a multi-layer ceramic capacitor (MLCC), is disposed in the cavity 104 and has electrodes 152, 154 disposed at its left and right ends, respectively. The remainder of cavity 104 may then be filled with resin 114 to secure capacitor 150 within substrate 100. The electrodes 152, 154 electrically connect with M1 metal layer 106 through a plurality of vias 116. Similarly, pads 152, 154 couple to M4 metal layer 112 through a plurality of vias 118.
Despite the reduced package footprint enabled by EPS capacitor 150 and its relatively short coupling distance to the associated die (not illustrated), there are a number of problems with such a conventional EPS approach. In particular, vias 116 as well as vias 118 are limited to the footprints for electrodes 152 and 154. The footprint (or surface area) of electrodes 152 and 154 thus limits the number of vias 116 and 118 that may be accommodated in package substrate 100. As the number of vias decrease, the current through each via increases and the resistance to the increased passage of current increases. Similarly, as current increases, the strength of the magnetic field increases and inductance associated with the current increases. The resulting parasitic inductance and resistance for the coupling to the associated die is thus undesirably high.
Accordingly, there is a need in the art for package substrates with embedded capacitors having reduced parasitic inductance and parasitic resistance.